"Analysis and Management of the Effects of Fluorinated Gases during Plasma Dicing" Janet Hopkins et al
(IMAPS-DPC 2021)
"Optimization of Low Temperature PECVD Dielectric Stacks for Via Reveal Passivation" K. Crook etc al
(IWLPC 2020)
"Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration" Anne Jourdain et al
(ECTC2020)
"Plasma Dicing: Reducing the cost of singulating thinner, smaller die" O. Ansell
(iMAPS MINAPAD 2017)
"Plasma Dicing 300mm Framed Wafers - Analysis of Improvement in Die Strength and Cost Benefits for for Thin Die Singulation" M. Blair
(ECTC 2017)
"Impact of Backside Processing on C-V Characteristics of TSV Capacitors in 3D stacked IC Process flows" J. de Vos et al
(EPTC 2015)
"Comparison between wet and dry silicon via reveal in 3D backside processing" D. Thomas et al; SPTS/imec joint paper
(IWLPC 2015)
"Wafer-to-Wafer Metal Sputter Deposition Process Control by Automatic Deposition Rate Adjustment" C. Weng et al
(CS Mantech 2015)
"Extending Capabilities of Etch and Deposition Technologies for 3D Packaging of MEMS in Volume Production" C Short et al
(IWLPC2014)
"Advances in Etch and Deposition Technologies for 2.5 and 3D BEOL Processing" K Buchanan et al
(SMTA Pan Pacific Symposium Conference 2014)
"Claritas™ – A unique and robust endpoint technology for silicon DRIE processes with open area down to 0.05%" O. Ansell et al
(MEMS2014)
"Advances in Back-side Via Etching of SiC for GaN Device Applications" A. Barker et al
(CS Mantech 2013)
"Plasma Etch and Low Temperature PECVD Processes for Via Reveal Applications" D. Thomas et al
(ECTC 2012)
"3D Multi-stacking of Thin Die based on TSV and Micro-inserts Interconnections" J. Souriau et al.
(ECTC 2012)
"Refractive Index Graded Anti-reflection Coating for Solar Cells Based on Low Cost Reclaimed Silicon" Y. Liu et al.
(MNE 2012)
"Advanced Deep Reactive-Ion Etching (DRIE) Technology for Hollow Microneedles for Transdermal Blood Sampling and Drug Delivery" Y. Liu et al.
(MNE 2011)
"Yield and Productivity Improvements Through Use of Advanced Dual Plasma Source for TSV Reveal & Wafer Dicing Applications" R. Barnett et al.
(EPTC 2011)
"300mm Scaling of Critical Silicon Etches for Image Sensor Wafer-Level Packaging Based on Tessera’s MVP (TSV) Technology" D.Thomas et al.
(IMAPS Device Packaging 2011)